摘要 :
To reduce the area and developing time of the Memory Built-in Self-Test (MBIST) circuit has been challenged in the market. An architecture that could test memories different in size by only one MBIST circuit is presented in this p...
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To reduce the area and developing time of the Memory Built-in Self-Test (MBIST) circuit has been challenged in the market. An architecture that could test memories different in size by only one MBIST circuit is presented in this paper. It is achieved by adding a data processing module and an address processing module into the mature and ready-made MBIST architecture. Base on this architecture, a MBIST circuit for the memories embedded in a SoC chip is successfully designed.
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摘要 :
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Efficien...
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Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Efficient yield-enhancement techniques for embedded memories thus are important for SOC. In this paper we present a built-in self-repair (BISR) scheme for semiconductor memories with 2-D redundancy structures. The BISR design is composed of a built-in self-test (BIST) module and a built-in redundancy analysis (BIRA) module. Our BIST circuit supports three test modes: the 1) main memory testing, 2) spare memory testing, and 3) repair modes. The BIRA module executes the proposed redundancy analysis (RA) algorithm for RAM with a 2-D redundancy structure, i.e., spare rows and spare columns. The BIRA module also serves as the reconfiguration (address remapping) unit in the normal mode. Experimental results show that a high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) is achieved with the proposed RA algorithm and BISR scheme. The BISR circuit has a low area overhead - about 4.6% for an 8K×64 SRAM.
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In this paper we describe a method to combine dictionary coding and partial LFSR reseeding to improve the ompression efficiency for test data compression. We also present a fast matrix calculation method which significantly reduce...
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In this paper we describe a method to combine dictionary coding and partial LFSR reseeding to improve the ompression efficiency for test data compression. We also present a fast matrix calculation method which significantly reduces the computation time to find a solution for partial LFSR reseeding. Experimental results on ISCAS89 benchmark circuits show that our approach is better than either dictionary coding or LFSR reseeding, and outperforms several test data compression methods proposed recently.
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New test point selection algorithms to improve test point insertion quality and performance of a multi-phase test point insertion scheme, while reducing the memory requirement of the analysis are proposed. A new memory efficient p...
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New test point selection algorithms to improve test point insertion quality and performance of a multi-phase test point insertion scheme, while reducing the memory requirement of the analysis are proposed. A new memory efficient probabilistic fault simulation method, which also handles the reconvergences to a limited extent for increased accuracy, is introduced. Synergistic control point insertion is targeted for higher test point insertion quality. Experiments conducted on various large industrial circuits demonstrate the effectiveness of the new algorithms.
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This article proposes an arbitrary waveform generator based on the Berlekamp-Massey Algorithm (BMA) modified to operate in the Real field. The main application for the proposed generator is in integrated mixed circuits test, parti...
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This article proposes an arbitrary waveform generator based on the Berlekamp-Massey Algorithm (BMA) modified to operate in the Real field. The main application for the proposed generator is in integrated mixed circuits test, particularly analog-to-digital converters. Simulations of the proposed generator were performed using MatLab® software. Results for different waveforms (input sequence) generated by the proposed generator is showed, applying different threshold values in BMA.
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摘要 :
This article proposes an arbitrary waveform generator based on the Berlekamp-Massey Algorithm (BMA) modified to operate in the Real field. The main application for the proposed generator is in integrated mixed circuits test, parti...
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This article proposes an arbitrary waveform generator based on the Berlekamp-Massey Algorithm (BMA) modified to operate in the Real field. The main application for the proposed generator is in integrated mixed circuits test, particularly analog-to-digital converters. Simulations of the proposed generator were performed using MatLab? software. Results for different waveforms (input sequence) generated by the proposed generator is showed, applying different threshold values in BMA.
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Wallace free summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex systems on chip. Testing of such multiplier cores deeply em...
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Wallace free summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex systems on chip. Testing of such multiplier cores deeply embedded in complex ICs requires the utilization of a BIST architecture that can be easily synthesized along with the multiplier by the module generator. In this paper we introduce an effective BIST architecture for fast multipliers that completely complies with this requirement. The algorithmic BIST patterns that this architecture generates guarantee a fault coverage higher than 99%. The required test pattern generator consists of a simple fixed-size binary counter, independent of the multiplier size. Accumulator-based compaction is adopted since multipliers and adders co-exist in most datapath architectures.
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Robust circuits are able to tolerate certain faults, but also pose additional challenges for test and diagnosis. To improve yield, the test must distinguish between critical faults and such faults, that could be compensated during...
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Robust circuits are able to tolerate certain faults, but also pose additional challenges for test and diagnosis. To improve yield, the test must distinguish between critical faults and such faults, that could be compensated during system operation, in addition, efficient diagnosis procedures are needed to support yield ramp-up in the case of critical faults. Previous work on circuits with time redundancy has shown that "signature rollback" can distinguish critical permanent faults from uncritical transient faults. The test is partitioned into shorter sessions, and a rollback is triggered immediately after a faulty session. If the repeated session shows the correct result, then a transient fault is assumed. The reference values for the sessions are represented in a very compact format. Storing only a few bits characterizing the MISR state over time can provide the same quality as storing the complete signature. In this work the signature rollback scheme is extended to an integrated test and diagnosis procedure. It is shown that a single test run with highly compacted reference data is sufficient to reach a comparable diagnostic resolution to that of a diagnostic session without any data compaction.
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摘要 :
Robust circuits are able to tolerate certain faults, but also pose additional challenges for test and diagnosis. To improve yield, the test must distinguish between critical faults and such faults, that could be compensated during...
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Robust circuits are able to tolerate certain faults, but also pose additional challenges for test and diagnosis. To improve yield, the test must distinguish between critical faults and such faults, that could be compensated during system operation, in addition, efficient diagnosis procedures are needed to support yield ramp-up in the case of critical faults. Previous work on circuits with time redundancy has shown that "signature rollback" can distinguish critical permanent faults from uncritical transient faults. The test is partitioned into shorter sessions, and a rollback is triggered immediately after a faulty session. If the repeated session shows the correct result, then a transient fault is assumed. The reference values for the sessions are represented in a very compact format. Storing only a few bits characterizing the MISR state over time can provide the same quality as storing the complete signature. In this work the signature rollback scheme is extended to an integrated test and diagnosis procedure. It is shown that a single test run with highly compacted reference data is sufficient to reach a comparable diagnostic resolution to that of a diagnostic session without any data compaction.
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